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WiringPi/wiringPi/khadas_edge.c

787 righe
22 KiB
Originale Blame Cronologia 

  1. /*----------------------------------------------------------------------------*/

  2. //

  3. //

  4. //	WiringPi KHADAS-EDGE Board Control file (ROCKCHIP 64Bits Platform)

  5. //

  6. //

  7. /*----------------------------------------------------------------------------*/

  8. #include <stdio.h>

  9. #include <stdlib.h>

  10. #include <stdint.h>

  11. #include <unistd.h>

  12. #include <errno.h>

  13. #include <string.h>

  14. #include <fcntl.h>

  15. #include <sys/ioctl.h>

  16. #include <asm/ioctl.h>

  17. #include <sys/mman.h>

  18. #include <sys/utsname.h>

  19. 

  20. /*----------------------------------------------------------------------------*/

  21. #include "softPwm.h"

  22. #include "softTone.h"

  23. 

  24. /*----------------------------------------------------------------------------*/

  25. #include "wiringPi.h"

  26. #include "khadas_edge.h"

  27. 

  28. /*----------------------------------------------------------------------------*/

  29. // wiringPi gpio map define

  30. /*----------------------------------------------------------------------------*/

  31. // Revision 2:

  32. static const int pinToGpio[64] = {

  33. 	// wiringPi number to native gpio number

  34. 	120,  121,	//  0 |  1 :            GPIO3_D0 | GPIO3_D1

  35. 	122,  123,	//  2 |  3 :            GPIO3_D2 | GPIO3_D3

  36. 	124,  125,	//  4 |  5 :            GPIO3_D4 | GPIO3_D5

  37. 	126,  127,	//  6 |  7 :            GPIO3_D6 | GPIO3_D7

  38. 	64,  65,	//  8 |  9 : (GPIO2_A0) I2C2_SDA | I2C2_SCL (GPIO2_A1)

  39. 	50, 128,	// 10 | 11 :  (GPIO1_C2) SPI3_CS | I2S_CLK (GPIO4_A0)

  40. 	47,  48,	// 12 | 13 : (GPIO1_B7) SPI3_TXD | SPI3_RXD (GPIO1_C0)

  41. 	49,  -1,	// 14 | 15 : (GPIO1_C1) SPI3_CLK | UART_TX

  42. 	-1, 112,	// 16 | 17 :             UART_RX | SPDIF_TX (GPIO3_C0)

  43. 	-1,  -1,	// 18 | 19 :

  44. 	-1,  -1,	// 20 | 21 :  

  45. 	-1,  -1,	// 22 | 23 : 

  46. 	-1,  -1,	// 24 | 25 : 					 | ADC_IN2

  47. 	-1,  -1,	// 26 | 27 : 

  48. 	-1,  -1,	// 28 | 29 : 					 | ADC_IN3

  49. 	-1,  -1,	// 30 | 31 : 

  50. 

  51. 	// Padding:

  52. 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	// 32...47

  53. 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,	// 48...63

  54. };

  55. 

  56. static const int phyToGpio[64] = {

  57. 	// physical header pin number to native gpio number

  58. 	 -1,		//  0

  59. 	 -1, -1,			//	 1 | 21 :						 5V | GND

  60. 	 -1, 48,			//	 2 | 22 :						 5V | SPI3_RXD (GPIO1_C0)

  61. 	 -1, 47,			//	 3 | 23 :				   HOST1_DM | SPI3_TXD (GPIO1_B7)

  62. 	 -1, -1,			//	 4 | 24 :				   HOST1_DP | GND

  63. 	 -1, 65,			//	 5 | 25 :						GND | I2C2_SCL (GPIO2_A1)

  64. 	 -1, 64,			//	 6 | 26 :					   3.3V | I2C2_SDA (GPIO2_A0)

  65. 	 -1, -1,			//	 7 | 27 :				   MCU_NRST | 3.3V

  66. 	 -1, -1,			//	 8 | 28 :				   MCU_SWIM | GND

  67. 	 -1,120,			//	 9 | 29 :						GND | I2S0_SCLK (GPIO3_D0)

  68. 	 -1,128,			//	10 | 30 :					ADC_IN2 | I2S_CLK (GPIO4_A0)

  69. 	 -1,127,			//	11 | 31 :					   1.8V | I2S0_SDO0 (GPIO3_D7)

  70. 	 -1,122,			//	12 | 32 :					ADC_IN3 | I2S0_LRCK_TX (GPIO3_D2)

  71. 	112,123,			//	13 | 33 :		(GPIO3_C0) SPDIF_TX | I2S0_SDI0 (GPIO3_D3)

  72. 	 -1, -1,			//	14 | 34 :						GND | GND

  73. 	 50,126,			//	15 | 35 :	     (GPIO1_C2) SPI3_CS | I2S0_SDI3SDO1 (GPIO3_D6)

  74. 	 49,125,			//	16 | 36 :	    (GPIO1_C1) SPI3_CLK | I2S0_SDI2SDO2 (GPIO3_D5)

  75. 	 -1,124,			//	17 | 37 :						GND | I2S0_SDI1SDO3 (GPIO3_D4)

  76. 	 -1,121,			//	18 | 38 :		            UART_RX | I2S0_LRCK_RX (GPIO3_D1)

  77. 	 -1, -1,			//	19 | 39 :		            UART_TX | MCU_PA1

  78. 	 -1, -1,			//	20 | 40 :					   3.3V | GND

  79. 

  80. 

  81. 	// Not used

  82. 	-1, -1, -1, -1, -1, -1, -1, -1,	// 41...48

  83. 	-1, -1, -1, -1, -1, -1, -1, -1,	// 49...56

  84. 	-1, -1, -1, -1, -1, -1, -1	// 57...63

  85. };

  86. 

  87. /*----------------------------------------------------------------------------*/

  88. //

  89. // Global variable define

  90. //

  91. /*----------------------------------------------------------------------------*/

  92. /* ADC file descriptor */

  93. static int adcFds[2];

  94. 

  95. /* GPIO mmap control. Actual GPIO bank number. */

  96. static volatile uint32_t *gpio[5];

  97. 

  98. /* GRF(General Register Files) base addresses to control GPIO modes */

  99. static volatile uint32_t *grf[2];

  100. 

  101. /* CRU(Clock & Reset Unit) base addresses to control CLK mode */

  102. static volatile uint32_t *cru[2];

  103. 

  104. /* wiringPi Global library */

  105. static struct libkhadas	*lib = NULL;

  106. 

  107. /*----------------------------------------------------------------------------*/

  108. // Function prototype define

  109. /*----------------------------------------------------------------------------*/

  110. static int	gpioToShiftReg	(int pin);

  111. static int	gpioToShiftGReg	(int pin);

  112. static void	setClkState	(int pin, int state);

  113. static void	setIomuxMode 	(int pin, int mode);

  114. 

  115. /*----------------------------------------------------------------------------*/

  116. // wiringPi core function

  117. /*----------------------------------------------------------------------------*/

  118. static int		_getModeToGpio		(int mode, int pin);

  119. static void		_pinMode		(int pin, int mode);

  120. static int		_getAlt			(int pin);

  121. static void		_pullUpDnControl	(int pin, int pud);

  122. static int		_digitalRead		(int pin);

  123. static void		_digitalWrite		(int pin, int value);

  124. static int		_analogRead		(int pin);

  125. static void		_digitalWriteByte	(const int value);

  126. static unsigned int	_digitalReadByte	(void);

  127. 

  128. /*----------------------------------------------------------------------------*/

  129. // board init function

  130. /*----------------------------------------------------------------------------*/

  131. static 	void init_gpio_mmap	(void);

  132. static 	void init_adc_fds	(void);

  133. 

  134. void init_khadas_edge 	(struct libkhadas *libwiring);

  135. 

  136. /*----------------------------------------------------------------------------*/

  137. /*----------------------------------------------------------------------------*/

  138. //

  139. // offset to the GPIO bit

  140. //

  141. /*----------------------------------------------------------------------------*/

  142. static int gpioToShiftReg (int pin)

  143. {

  144. 	return pin % 32;

  145. }

  146. 

  147. /*----------------------------------------------------------------------------*/

  148. //

  149. // offset to the GPIO bit at GRF address

  150. //

  151. /*----------------------------------------------------------------------------*/

  152. static int gpioToShiftGReg (int pin)

  153. {

  154. 	return pin % 8;

  155. }

  156. 

  157. /*----------------------------------------------------------------------------*/

  158. static int _getModeToGpio (int mode, int pin)

  159. {

  160. 	if (pin > 255)

  161. 		return msg(MSG_ERR, "%s : Invalid pin number %d\n", __func__, pin);

  162. 

  163. 	switch (mode) {

  164. 	/* Native gpio number */

  165. 	case	MODE_GPIO:

  166. 		return	pin;

  167. 	/* Native gpio number for sysfs */

  168. 	case	MODE_GPIO_SYS:

  169. 		return	lib->sysFds[pin] != -1 ? pin : -1;

  170. 	/* wiringPi number */

  171. 	case	MODE_PINS:

  172. 		return	pin < 64 ? pinToGpio[pin] : -1;

  173. 	/* header pin number */

  174. 	case	MODE_PHYS:

  175. 		return	pin < 64 ? phyToGpio[pin] : -1;

  176. 	default	:

  177. 		msg(MSG_WARN, "%s : Unknown Mode %d\n", __func__, mode);

  178. 		return	-1;

  179. 	}

  180. }

  181. 

  182. /*----------------------------------------------------------------------------*/

  183. //

  184. // set GPIO clock state

  185. //

  186. /*----------------------------------------------------------------------------*/

  187. static void setClkState (int pin, int state)

  188. {

  189. 	uint32_t target = 0;

  190. 	uint8_t bank = pin / 32;

  191. 	uint8_t shift = bank < 2 ? bank + 2 : bank + 1;

  192. 

  193. 	target |= (1 << (shift + 16));

  194. 

  195. 	switch (state) {

  196. 	case EDGE_CLK_ENABLE:

  197. 		if (bank < 2) {

  198. 			target |= *(cru[0] + (EDGE_PMUCRU_GPIO_CLK_OFFSET >> 2));

  199. 			target &= ~(1 << shift);

  200. 			*(cru[0] + (EDGE_PMUCRU_GPIO_CLK_OFFSET >> 2)) = target;

  201. 		} else {

  202. 			target |= *(cru[1] + (EDGE_CRU_GPIO_CLK_OFFSET >> 2));

  203. 			target &= ~(1 << shift);

  204. 			*(cru[1] + (EDGE_CRU_GPIO_CLK_OFFSET >> 2)) = target;

  205. 		}

  206. 		break;

  207. 	case EDGE_CLK_DISABLE:

  208. 		if (bank < 2) {

  209. 			target |= *(cru[0] + (EDGE_PMUCRU_GPIO_CLK_OFFSET >> 2));

  210. 			target |=  (1 << shift);

  211. 			*(cru[0] + (EDGE_PMUCRU_GPIO_CLK_OFFSET >> 2)) = target;

  212. 		} else {

  213. 			target |= *(cru[1] + (EDGE_CRU_GPIO_CLK_OFFSET >> 2));

  214. 			target |=  (1 << shift);

  215. 			*(cru[1] + (EDGE_CRU_GPIO_CLK_OFFSET >> 2)) = target;

  216. 		}

  217. 		break;

  218. 	default:

  219. 		break;

  220. 	}

  221. }

  222. 

  223. /*----------------------------------------------------------------------------*/

  224. //

  225. // set IOMUX mode

  226. //

  227. /*----------------------------------------------------------------------------*/

  228. static void setIomuxMode (int pin, int mode)

  229. {

  230. 	uint32_t offset, target;

  231. 	uint8_t	bank, group;

  232. 

  233. 	bank	= pin / 32;

  234. 	group	= (pin - bank * 32) / 8;

  235. 	offset	= 0x10 * (bank > 1 ? bank - 2 : bank) + 0x4 * group;

  236. 	target	= 0;

  237. 

  238. 	target |= (1 << (gpioToShiftGReg(pin) * 2 + 17));

  239. 	target |= (1 << (gpioToShiftGReg(pin) * 2 + 16));

  240. 

  241. 	switch (mode) {

  242. 	case EDGE_FUNC_GPIO:

  243. 		// Common IOMUX Funtion 1 : GPIO (0b00)

  244. 		if (bank < 2) {

  245. 			offset += EDGE_PMUGRF_IOMUX_OFFSET;

  246. 

  247. 			target |= *(grf[0] + (offset >> 2));

  248. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  249. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  250. 

  251. 			*(grf[0] + (offset >> 2)) = target;

  252. 		} else {

  253. 			offset += EDGE_GRF_IOMUX_OFFSET;

  254. 

  255. 			target |= *(grf[1] + (offset >> 2));

  256. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  257. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  258. 

  259. 			*(grf[1] + (offset >> 2)) = target;

  260. 		}

  261. 		break;

  262. 	default:

  263. 		break;

  264. 	}

  265. }

  266. 

  267. /*----------------------------------------------------------------------------*/

  268. static void _pinMode (int pin, int mode)

  269. {

  270. 	int origPin, bank;

  271. 	unsigned long UNU flags;

  272. 

  273. 	if (lib->mode == MODE_GPIO_SYS)

  274. 		return;

  275. 

  276. 	if ((pin = _getModeToGpio(lib->mode, pin)) < 0)

  277. 		return;

  278. 

  279. 	origPin = pin;

  280. 	bank = pin / 32;

  281. 

  282. 	softPwmStop (origPin);

  283. 	softToneStop(origPin);

  284. 

  285. 	setClkState (pin, EDGE_CLK_ENABLE);

  286. 	setIomuxMode(pin, EDGE_FUNC_GPIO);

  287. 

  288. 	switch (mode) {

  289. 	case INPUT:

  290. 		*(gpio[bank] + (EDGE_GPIO_CON_OFFSET >> 2)) &= ~(1 << gpioToShiftReg(pin));

  291. 		break;

  292. 	case OUTPUT:

  293. 		*(gpio[bank] + (EDGE_GPIO_CON_OFFSET >> 2)) |=  (1 << gpioToShiftReg(pin));

  294. 		break;

  295. 	case SOFT_PWM_OUTPUT:

  296. 		softPwmCreate (origPin, 0, 100);

  297. 		break;

  298. 	case SOFT_TONE_OUTPUT:

  299. 		softToneCreate (origPin);

  300. 		break;

  301. 	default:

  302. 		msg(MSG_WARN, "%s : Unknown Mode %d\n", __func__, mode);

  303. 		return;

  304. 	}

  305. 

  306. 	setClkState (pin, EDGE_CLK_DISABLE);

  307. }

  308. 

  309. /*----------------------------------------------------------------------------*/

  310. static int _getAlt (int pin)

  311. {

  312. 	uint32_t offset;

  313. 	uint8_t	bank, group, shift;

  314. 	uint8_t ret = 0;

  315. 

  316. 	if (lib->mode == MODE_GPIO_SYS)

  317. 		return	-1;

  318. 

  319. 	if ((pin = _getModeToGpio(lib->mode, pin)) < 0)

  320. 		return	-1;

  321. 

  322. 	bank	= pin / 32;

  323. 	group	= (pin - bank * 32) / 8;

  324. 	offset	= 0x10 * (bank > 1 ? bank - 2 : bank) + 0x4 * group;

  325. 	shift	= gpioToShiftGReg(pin) << 1;

  326. 

  327. 	setClkState(pin, EDGE_CLK_ENABLE);

  328. 

  329. 	// Check if the pin is GPIO mode on GRF register

  330. 	if (bank < 2) {

  331. 		offset += EDGE_PMUGRF_IOMUX_OFFSET;

  332. 		ret = (*(grf[0] + (offset >> 2)) >> shift) & 0b11;

  333. 	} else {

  334. 		offset += EDGE_GRF_IOMUX_OFFSET;

  335. 		ret = (*(grf[1] + (offset >> 2)) >> shift) & 0b11;

  336. 	}

  337. 

  338. 	// If it is GPIO mode, check it's direction

  339. 	if (ret == 0)

  340. 		ret = *(gpio[bank] + (EDGE_GPIO_CON_OFFSET >> 2)) & (1 << gpioToShiftReg(pin)) ? 1 : 0;

  341. 	else {

  342. 		// ALT1 is GPIO mode(0b00) on this SoC

  343. 		ret++;

  344. 	}

  345. 

  346. 	setClkState(pin, EDGE_CLK_DISABLE);

  347. 

  348. 	return ret;

  349. }

  350. 

  351. /*----------------------------------------------------------------------------*/

  352. static void _pullUpDnControl (int pin, int pud)

  353. {

  354. 	uint32_t offset, target;

  355. 	uint8_t	bank, group;

  356. 

  357. 	if (lib->mode == MODE_GPIO_SYS)

  358. 		return;

  359. 

  360. 	if ((pin = _getModeToGpio(lib->mode, pin)) < 0)

  361. 		return;

  362. 

  363. 	bank	= pin / 32;

  364. 	group	= (pin - bank * 32) / 8;

  365. 	offset	= 0x10 * (bank > 1 ? bank - 2 : bank) + 0x4 * group;

  366. 	target	= 0;

  367. 

  368. 	target |= (1 << (gpioToShiftGReg(pin) * 2 + 17));

  369. 	target |= (1 << (gpioToShiftGReg(pin) * 2 + 16));

  370. 

  371. 	setClkState(pin, EDGE_CLK_ENABLE);

  372. 

  373. 	switch (pud) {

  374. 	case PUD_UP:

  375. 		if (bank < 2) {

  376. 			offset += EDGE_PMUGRF_PUPD_OFFSET;

  377. 

  378. 			target |= *(grf[0] + (offset >> 2));

  379. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  380. 			target |=  (1 << (gpioToShiftGReg(pin) * 2));

  381. 

  382. 			*(grf[0] + (offset >> 2)) = target;

  383. 		} else {

  384. 			offset += EDGE_GRF_PUPD_OFFSET;

  385. 

  386. 			target |= *(grf[1] + (offset >> 2));

  387. 			if (bank == 2 && group >= 2) {

  388. 				target |=  (1 << (gpioToShiftGReg(pin) * 2 + 1));

  389. 				target |=  (1 << (gpioToShiftGReg(pin) * 2));

  390. 			} else {

  391. 				target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  392. 				target |=  (1 << (gpioToShiftGReg(pin) * 2));

  393. 			}

  394. 

  395. 			*(grf[1] + (offset >> 2)) = target;

  396. 		}

  397. 		break;

  398. 	case PUD_DOWN:

  399. 		if (bank < 2) {

  400. 			offset += EDGE_PMUGRF_PUPD_OFFSET;

  401. 

  402. 			target |= *(grf[0] + (offset >> 2));

  403. 			target |=  (1 << (gpioToShiftGReg(pin) * 2 + 1));

  404. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  405. 

  406. 			*(grf[0] + (offset >> 2)) = target;

  407. 		} else {

  408. 			offset += EDGE_GRF_PUPD_OFFSET;

  409. 

  410. 			target |= *(grf[1] + (offset >> 2));

  411. 			if (bank == 2 && group >= 2) {

  412. 				target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  413. 				target |=  (1 << (gpioToShiftGReg(pin) * 2));

  414. 			} else {

  415. 				target |=  (1 << (gpioToShiftGReg(pin) * 2 + 1));

  416. 				target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  417. 			}

  418. 

  419. 			*(grf[1] + (offset >> 2)) = target;

  420. 		}

  421. 		break;

  422. 	case PUD_OFF:

  423. 		if (bank < 2) {

  424. 			offset += EDGE_PMUGRF_PUPD_OFFSET;

  425. 

  426. 			target |= *(grf[0] + (offset >> 2));

  427. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  428. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  429. 

  430. 			*(grf[0] + (offset >> 2)) = target;

  431. 		} else {

  432. 			offset += EDGE_GRF_PUPD_OFFSET;

  433. 

  434. 			target |= *(grf[1] + (offset >> 2));

  435. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2 + 1));

  436. 			target &= ~(1 << (gpioToShiftGReg(pin) * 2));

  437. 

  438. 			*(grf[1] + (offset >> 2)) = target;

  439. 		}

  440. 		break;

  441. 	default:

  442. 		break;

  443. 	}

  444. 

  445. 	setClkState(pin, EDGE_CLK_DISABLE);

  446. }

  447. 

  448. /*----------------------------------------------------------------------------*/

  449. static int _digitalRead (int pin)

  450. {

  451. 	int bank, ret;

  452. 	char c;

  453. 

  454. 	if (lib->mode == MODE_GPIO_SYS) {

  455. 		if (lib->sysFds[pin] == -1)

  456. 			return -1;

  457. 

  458. 		lseek	(lib->sysFds[pin], 0L, SEEK_SET);

  459. 		if (read(lib->sysFds[pin], &c, 1) < 0) {

  460. 			msg(MSG_WARN, "%s: Failed with reading from sysfs GPIO node. \n", __func__);

  461. 			return -1;

  462. 		}

  463. 

  464. 		return (c == '0') ? LOW : HIGH;

  465. 	}

  466. 

  467. 	if ((pin = _getModeToGpio(lib->mode, pin)) < 0)

  468. 		return	-1;

  469. 

  470. 	bank = pin / 32;

  471. 	setClkState(pin, EDGE_CLK_ENABLE);

  472. 

  473. 	ret = *(gpio[bank] + (EDGE_GPIO_GET_OFFSET >> 2)) & (1 << gpioToShiftReg(pin)) ? HIGH : LOW;

  474. 

  475. 	setClkState(pin, EDGE_CLK_DISABLE);

  476. 	return ret;

  477. }

  478. 

  479. /*----------------------------------------------------------------------------*/

  480. static void _digitalWrite (int pin, int value)

  481. {

  482. 	int bank;

  483. 

  484. 	if (lib->mode == MODE_GPIO_SYS) {

  485. 		if (lib->sysFds[pin] != -1) {

  486. 			if (value == LOW) {

  487. 				if (write (lib->sysFds[pin], "0\n", 2) < 0)

  488. 					msg(MSG_ERR,

  489. 					"%s : %s\nEdit direction file to output mode for\n\t/sys/class/gpio/gpio%d/direction\n",

  490. 					__func__, strerror(errno), pin + EDGE_GPIO_PIN_BASE);

  491. 			} else {

  492. 				if (write (lib->sysFds[pin], "1\n", 2) < 0)

  493. 					msg(MSG_ERR,

  494. 					"%s : %s\nEdit direction file to output mode for\n\t/sys/class/gpio/gpio%d/direction\n",

  495. 					__func__, strerror(errno), pin + EDGE_GPIO_PIN_BASE);

  496. 			}

  497. 		}

  498. 		return;

  499. 	}

  500. 

  501. 	if ((pin = _getModeToGpio(lib->mode, pin)) < 0)

  502. 		return;

  503. 

  504. 	bank = pin / 32;

  505. 	setClkState(pin, EDGE_CLK_ENABLE);

  506. 

  507. 	switch (value) {

  508. 	case LOW:

  509. 		*(gpio[bank] + (EDGE_GPIO_SET_OFFSET >> 2)) &= ~(1 << gpioToShiftReg(pin));

  510. 		break;

  511. 	case HIGH:

  512. 		*(gpio[bank] + (EDGE_GPIO_SET_OFFSET >> 2)) |=  (1 << gpioToShiftReg(pin));

  513. 		break;

  514. 	default:

  515. 		break;

  516. 	}

  517. 

  518. 	setClkState(pin, EDGE_CLK_DISABLE);

  519. }

  520. 

  521. /*----------------------------------------------------------------------------*/

  522. static int _analogRead (int pin)

  523. {

  524. 	char value[5] = {0,};

  525. 

  526. 	if (lib->mode == MODE_GPIO_SYS)

  527. 		return	-1;

  528. 

  529. 	/* wiringPi ADC number = pin 25, pin 29 */

  530. 	switch (pin) {

  531. #if defined(ARDUINO)

  532. 	/* To work with physical analog channel numbering */

  533. 	case	1:	case	25:

  534. 		pin = 0;

  535. 	break;

  536. 	case	0:	case	29:

  537. 		pin = 1;

  538. 	break;

  539. #else

  540. 	case	0:	case	25:

  541. 		pin = 0;

  542. 	break;

  543. 	case	1:	case	29:

  544. 		pin = 1;

  545. 	break;

  546. #endif

  547. 	default:

  548. 		return	0;

  549. 	}

  550. 	if (adcFds [pin] == -1)

  551. 		return 0;

  552. 

  553. 	lseek(adcFds [pin], 0L, SEEK_SET);

  554. 	if (read(adcFds [pin], &value[0], 4) < 0) {

  555. 		msg(MSG_WARN, "%s: Error occurs when it reads from ADC file descriptor. \n", __func__);

  556. 		return -1;

  557. 	}

  558. 

  559. 	return	atoi(value);

  560. }

  561. 

  562. /*----------------------------------------------------------------------------*/

  563. static void _digitalWriteByte (const int value)

  564. {

  565. 	union	reg_bitfield	gpioBits3;

  566. 

  567. 	if (lib->mode == MODE_GPIO_SYS) {

  568. 		return;

  569. 	}

  570. 

  571. 	// Enable clock for GPIO 1 bank

  572. 	setClkState(96, EDGE_CLK_ENABLE);

  573. 

  574. 	/* Read data register */

  575. 	gpioBits3.wvalue = *(gpio[3] + (EDGE_GPIO_GET_OFFSET >> 2));

  576. 

  577. 	/* Wiring PI GPIO0 = EDGE GPIO3_D.0 */

  578. 	gpioBits3.bits.bit0  = (value & 0x01);

  579. 	/* Wiring PI GPIO1 = EDGE GPIO3_D.1 */

  580. 	gpioBits3.bits.bit1  = (value & 0x02);

  581. 	/* Wiring PI GPIO2 = EDGE GPIO3_D.2 */

  582. 	gpioBits3.bits.bit2  = (value & 0x04);

  583. 	/* Wiring PI GPIO3 = EDGE GPIO3_D.3 */

  584. 	gpioBits3.bits.bit3  = (value & 0x08);

  585. 	/* Wiring PI GPIO4 = EDGE GPIO3_D.4 */

  586. 	gpioBits3.bits.bit4 = (value & 0x10);

  587. 	/* Wiring PI GPIO5 = EDGE GPIO3_D.5 */

  588. 	gpioBits3.bits.bit5 = (value & 0x20);

  589. 	/* Wiring PI GPIO6 = EDGE GPIO3_D.6 */

  590. 	gpioBits3.bits.bit6 = (value & 0x40);

  591. 	/* Wiring PI GPIO7 = EDGE GPIO3_D.7 */

  592. 	gpioBits3.bits.bit7  = (value & 0x80);

  593. 

  594. 	/* Update data register */

  595. 	*(gpio[3] + (EDGE_GPIO_SET_OFFSET >> 2)) = gpioBits3.wvalue;

  596. 

  597. 	setClkState(96, EDGE_CLK_DISABLE);

  598. }

  599. 

  600. /*----------------------------------------------------------------------------*/

  601. static unsigned int _digitalReadByte (void)

  602. {

  603. 	union reg_bitfield	gpioBits3;

  604. 	unsigned int		value = 0;

  605. 

  606. 	if (lib->mode == MODE_GPIO_SYS) {

  607. 		return	-1;

  608. 	}

  609. 

  610. 	// Enable clock for GPIO 1 bank

  611. 	setClkState(96, EDGE_CLK_ENABLE);

  612. 

  613. 	/* Read data register */

  614. 	gpioBits3.wvalue = *(gpio[3] + (EDGE_GPIO_GET_OFFSET >> 2));

  615. 

  616. 	setClkState(96, EDGE_CLK_DISABLE);

  617. 

  618. 	/* Wiring PI GPIO0 = EDGE GPIO3_D.0 */

  619. 	if (gpioBits3.bits.bit0)

  620. 		value |= 0x01;

  621. 	/* Wiring PI GPIO1 = EDGE GPIO3_D.1 */

  622. 	if (gpioBits3.bits.bit1)

  623. 		value |= 0x02;

  624. 	/* Wiring PI GPIO2 = EDGE GPIO3_D.2 */

  625. 	if (gpioBits3.bits.bit2)

  626. 		value |= 0x04;

  627. 	/* Wiring PI GPIO3 = EDGE GPIO3_D.3 */

  628. 	if (gpioBits3.bits.bit3)

  629. 		value |= 0x08;

  630. 	/* Wiring PI GPIO4 = EDGE GPIO3_D.4 */

  631. 	if (gpioBits3.bits.bit4)

  632. 		value |= 0x10;

  633. 	/* Wiring PI GPIO5 = EDGE GPIO3_D.5 */

  634. 	if (gpioBits3.bits.bit5)

  635. 		value |= 0x20;

  636. 	/* Wiring PI GPIO6 = EDGE GPIO3_D.6 */

  637. 	if (gpioBits3.bits.bit6)

  638. 		value |= 0x40;

  639. 	/* Wiring PI GPIO7 = EDGE GPIO3_D.7 */

  640. 	if (gpioBits3.bits.bit7)

  641. 		value |= 0x80;

  642. 

  643. 	return value;

  644. }

  645. 

  646. /*----------------------------------------------------------------------------*/

  647. static void init_gpio_mmap (void)

  648. {

  649. 	int fd = -1;

  650. 	void *mapped_cru[2], *mapped_grf[2], *mapped_gpio[5];

  651. 

  652. 	/* GPIO mmap setup */

  653. 	if (!getuid()) {

  654. 		if ((fd = open ("/dev/mem", O_RDWR | O_SYNC | O_CLOEXEC) ) < 0)

  655. 			msg (MSG_ERR,

  656. 				"wiringPiSetup: Unable to open /dev/mem: %s\n",

  657. 				strerror (errno));

  658. 	} else {

  659. 		if (access("/dev/gpiomem",0) == 0) {

  660. 			if ((fd = open ("/dev/gpiomem", O_RDWR | O_SYNC | O_CLOEXEC) ) < 0)

  661. 				msg (MSG_ERR,

  662. 					"wiringPiSetup: Unable to open /dev/gpiomem: %s\n",

  663. 					strerror (errno));

  664. 		} else

  665. 			msg (MSG_ERR,

  666. 				"wiringPiSetup: /dev/gpiomem doesn't exist. Please try again with sudo.\n");

  667. 	}

  668. 

  669. 	if (fd < 0) {

  670. 		msg(MSG_ERR, "wiringPiSetup: Cannot open memory area for GPIO use. \n");

  671. 	} else {

  672. 		// GPIO{0, 1}

  673. 		//#define EDGE_PMUCRU_BASE	0xFF750000

  674. 		mapped_cru[0] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_PMUCRU_BASE);

  675. 

  676. 		// GPIO{2, 3, 4}

  677. 		//#define EDGE_CRU_BASE	0xFF760000

  678. 		mapped_cru[1] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_CRU_BASE);

  679. 

  680. 		// GPIO{0, 1}

  681. 		//#define EDGE_PMU_BASE	0xFF320000

  682. 		mapped_grf[0] = mmap(0, EDGE_GRF_BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_PMUGRF_BASE);

  683. 

  684. 		// GPIO{2, 3, 4}

  685. 		//#define EDGE_GRF_BASE	0xFF770000

  686. 		mapped_grf[1] = mmap(0, EDGE_GRF_BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GRF_BASE);

  687. 

  688. 		// GPIO1_A.	0,1,2,3,4,7

  689. 		// GPIO1_B.	0,1,2,3,4,5

  690. 		// GPIO1_C.	2,4,5,6

  691. 		// GPIO1_D.	0

  692. 		//#define EDGE_GPIO1_BASE	0xFF730000

  693. 		mapped_gpio[1] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GPIO_1_BASE);

  694. 

  695. 		// GPIO2_C.	0_B,1_B

  696. 		//#define EDGE_GPIO2_BASE	0xFF780000

  697. 		mapped_gpio[2] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GPIO_2_BASE);

  698. 

  699. 		// GPIO4_C.	5,6

  700. 		// GPIO4_D.	0,4,5,6

  701. 		//#define EDGE_GPIO4_BASE	0xFF790000

  702. 		mapped_gpio[4] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GPIO_4_BASE);

  703. 

  704. 		// Reserved

  705. 		mapped_gpio[0] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GPIO_0_BASE);

  706. 		mapped_gpio[3] = mmap(0, BLOCK_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, EDGE_GPIO_3_BASE);

  707. 

  708. 		if ((mapped_cru[0] == MAP_FAILED) || (mapped_cru[1] == MAP_FAILED)) {

  709. 			msg (MSG_ERR,

  710. 				"wiringPiSetup: mmap (CRU) failed: %s\n",

  711. 				strerror (errno));

  712. 		} else {

  713. 			cru[0] = (uint32_t *) mapped_cru[0];

  714. 			cru[1] = (uint32_t *) mapped_cru[1];

  715. 		}

  716. 

  717. 		if ((mapped_grf[0] == MAP_FAILED) || (mapped_grf[1] == MAP_FAILED)) {

  718. 			msg (MSG_ERR,

  719. 				"wiringPiSetup: mmap (GRF) failed: %s\n",

  720. 				strerror (errno));

  721. 		} else {

  722. 			grf[0] = (uint32_t *) mapped_grf[0];

  723. 			grf[1] = (uint32_t *) mapped_grf[1];

  724. 		}

  725. 

  726. 		if (	(mapped_gpio[0] == MAP_FAILED) ||

  727. 			(mapped_gpio[1] == MAP_FAILED) ||

  728. 			(mapped_gpio[2] == MAP_FAILED) ||

  729. 			(mapped_gpio[3] == MAP_FAILED) ||

  730. 			(mapped_gpio[4] == MAP_FAILED)) {

  731. 			msg (MSG_ERR,

  732. 				"wiringPiSetup: mmap (GPIO) failed: %s\n",

  733. 				strerror (errno));

  734. 		} else {

  735. 			gpio[0] = (uint32_t *) mapped_gpio[0];

  736. 			gpio[1] = (uint32_t *) mapped_gpio[1];

  737. 			gpio[2] = (uint32_t *) mapped_gpio[2];

  738. 			gpio[3] = (uint32_t *) mapped_gpio[3];

  739. 			gpio[4] = (uint32_t *) mapped_gpio[4];

  740. 		}

  741. 	}

  742. }

  743. 

  744. /*----------------------------------------------------------------------------*/

  745. static void init_adc_fds (void)

  746. {

  747. 	const char *AIN0_NODE, *AIN1_NODE;

  748. 	struct utsname uname_buf;

  749. 

  750. 	/* ADC node setup */

  751. 	uname(&uname_buf);

  752. 

  753. 	AIN0_NODE = "/sys/devices/platform/ff100000.saradc/iio:device0/in_voltage2_raw";

  754. 	AIN1_NODE = "/sys/devices/platform/ff100000.saradc/iio:device0/in_voltage3_raw";

  755. 

  756. 	adcFds[0] = open(AIN0_NODE, O_RDONLY);

  757. 	adcFds[1] = open(AIN1_NODE, O_RDONLY);

  758. }

  759. 

  760. /*----------------------------------------------------------------------------*/

  761. void init_khadas_edge (struct libkhadas *libwiring)

  762. {

  763. 	init_gpio_mmap();

  764. 

  765. 	init_adc_fds();

  766. 

  767. 	/* wiringPi Core function initialize */

  768. 	libwiring->getModeToGpio	= _getModeToGpio;

  769. 	libwiring->pinMode		= _pinMode;

  770. 	libwiring->getAlt		= _getAlt;

  771. 	libwiring->pullUpDnControl	= _pullUpDnControl;

  772. 	libwiring->digitalRead		= _digitalRead;

  773. 	libwiring->digitalWrite		= _digitalWrite;

  774. 	libwiring->analogRead		= _analogRead;

  775. 	libwiring->digitalWriteByte	= _digitalWriteByte;

  776. 	libwiring->digitalReadByte	= _digitalReadByte;

  777. 

  778. 	/* specify pin base number */

  779. 	libwiring->pinBase		= EDGE_GPIO_PIN_BASE;

  780. 

  781. 	/* global variable setup */

  782. 	lib = libwiring;

  783. }

  784. 

  785. /*----------------------------------------------------------------------------*/

  786. /*----------------------------------------------------------------------------*/